diff --git a/src/main.rs b/src/main.rs
index 6f0d6d5..3b2d764 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -48,7 +48,7 @@ unsafe extern "C" fn _enter() -> ! {
         "csrw mtvec, t1",
 
         // Set MSIE, MTIE, and MEIE on machine interrupt enable CSR:
-        //   (1 << 3)   = MSIE to enable machine-/M-mode software interrupts
+        //   (1 << 3) = MSIE to enable machine-/M-mode software interrupts
         //   | (1 << 7) = MTIE to enable M-mode timer interrupts (disabled for now)
         //   | (1 << 11) = MEIE to enable M-mode external interrupts
         "li t2, (1 << 3) | (1 << 11)",