From 20c0841a8913ba181077644858096d01cb899a70 Mon Sep 17 00:00:00 2001
From: gil <kalanggam@proton.me>
Date: Sat, 18 May 2024 08:00:48 -0500
Subject: [PATCH] Enable other cores and rewrite init step

---
 .cargo/config.toml | 1 +
 src/main.rs        | 7 ++++---
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/.cargo/config.toml b/.cargo/config.toml
index 92a6f91..c7c38b4 100644
--- a/.cargo/config.toml
+++ b/.cargo/config.toml
@@ -18,6 +18,7 @@ target = "riscv64imac-unknown-none-elf"
 [target.riscv64imac-unknown-none-elf]
 runner = """ qemu-system-riscv64
   -cpu rv64
+  -smp 4
   -machine virt
   -m 150M
   -s
diff --git a/src/main.rs b/src/main.rs
index 7ff4b9d..cf4c847 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -16,9 +16,10 @@ unsafe extern "C" fn _enter() -> ! {
     // TODO see if possible to replace this somehow...
     use core::arch::asm;
     asm!(
-        // load hartid into t0; if t0 =/= 0, then jump to busy loop
-        "csrr t0, mhartid",
-        "bnez t0, 3f",
+        // load hartid into `tp``
+        // if hartid =/= 0, then jump to busy loop
+        "csrr tp, mhartid",
+        "bnez tp, 3f",
 
         // before we use the `la` pseudo-instruction for the first time,
         // we need to set `gp` (look up linker relaxation)