Trying to figure stuff out

lds/kernel.lds

@@ -4,7 +4,7 @@ OUTPUT_ARCH("riscv")
 ENTRY(_entry)
 
 MEMORY {
-  ram   (wxa) : ORIGIN = 0x80000000, LENGTH = 128M
+  ram (wxa) : ORIGIN = 0x80000000, LENGTH = 128M
 }
 
 PHDRS {

src/main.rs

@@ -15,9 +15,10 @@ core::arch::global_asm!(include_str!("entry.s"));
 /// After some initialization in asm/entry.s, the kernel will jump here and
 /// each hart will have its own setup sequence.
 #[no_mangle]
+#[allow(unreachable_code)]
 unsafe extern "C" fn start() {
     use core::arch::asm;
-    use riscv::register::{mepc, mstatus, satp, sie, sstatus};
+    use riscv::register::{mstatus, pmpaddr0, satp, sie, sstatus};
 
     // Set previous privilege for all harts to M-mode, set previous interrupt
     // enable, and set floating-point unit to initial state
@@ -37,22 +38,24 @@ unsafe extern "C" fn start() {
     sie::set_stimer();
     sie::set_ssoft();
 
+    // hhhh
+    // pmpaddr0::write(0x3fffffffffffff_usize);
     // TODO configure PMP
     // TODO timer init
 
     // Trying to figure out why I can't use mret here. Might need
     // asm!(
-    //     "la t1, 1f",
+    //     "la t1, main",
     //     "csrw mepc, t1",
-    //     "la ra, 1f",
     //     "mret",
-    // "1:",
+    //     options(noreturn),
     // );
 
     main();
 }
 
-fn main() {
+#[no_mangle]
+extern "C" fn main() {
     use riscv::interrupt;
     use riscv::register::{mstatus, sstatus};