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Trying to figure stuff out

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gil 2024-05-23 14:10:40 -05:00
parent 4edcebba18
commit 6f6f012be9
2 changed files with 9 additions and 6 deletions
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13
src/main.rs
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@ -15,9 +15,10 @@ core::arch::global_asm!(include_str!("entry.s"));
/// After some initialization in asm/entry.s, the kernel will jump here and /// After some initialization in asm/entry.s, the kernel will jump here and
/// each hart will have its own setup sequence. /// each hart will have its own setup sequence.
#[no_mangle] #[no_mangle]
#[allow(unreachable_code)]
unsafe extern "C" fn start() { unsafe extern "C" fn start() {
use core::arch::asm; use core::arch::asm;
use riscv::register::{mepc, mstatus, satp, sie, sstatus}; use riscv::register::{mstatus, pmpaddr0, satp, sie, sstatus};
// Set previous privilege for all harts to M-mode, set previous interrupt // Set previous privilege for all harts to M-mode, set previous interrupt
// enable, and set floating-point unit to initial state // enable, and set floating-point unit to initial state
@ -37,22 +38,24 @@ unsafe extern "C" fn start() {
sie::set_stimer(); sie::set_stimer();
sie::set_ssoft(); sie::set_ssoft();
// hhhh
// pmpaddr0::write(0x3fffffffffffff_usize);
// TODO configure PMP // TODO configure PMP
// TODO timer init // TODO timer init
// Trying to figure out why I can't use mret here. Might need // Trying to figure out why I can't use mret here. Might need
// asm!( // asm!(
// "la t1, 1f", // "la t1, main",
// "csrw mepc, t1", // "csrw mepc, t1",
// "la ra, 1f",
// "mret", // "mret",
// "1:", // options(noreturn),
// ); // );
main(); main();
} }
fn main() { #[no_mangle]
extern "C" fn main() {
use riscv::interrupt; use riscv::interrupt;
use riscv::register::{mstatus, sstatus}; use riscv::register::{mstatus, sstatus};