From 7f183c771297982be990eeacbdafffe0f8206179 Mon Sep 17 00:00:00 2001 From: gil Date: Fri, 17 May 2024 10:40:55 -0500 Subject: [PATCH] Fixed kernel hanging by disabling timer interrupts --- src/main.rs | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/main.rs b/src/main.rs index 026a758..6f0d6d5 100644 --- a/src/main.rs +++ b/src/main.rs @@ -48,11 +48,11 @@ unsafe extern "C" fn _enter() -> ! { "csrw mtvec, t1", // Set MSIE, MTIE, and MEIE on machine interrupt enable CSR: - // MSIE to enable machine-/M-mode software interrupts - // MTIE to enable M-mode timer interrupts - // MEIE to enable M-mode external interrupts - //"li t2, (1 << 3) | (1 << 7) | (1 << 11)", - //"csrw mie, t2", -> This is causing problems - after setting this register the kernel hangs + // (1 << 3) = MSIE to enable machine-/M-mode software interrupts + // | (1 << 7) = MTIE to enable M-mode timer interrupts (disabled for now) + // | (1 << 11) = MEIE to enable M-mode external interrupts + "li t2, (1 << 3) | (1 << 11)", + "csrw mie, t2", // clear the BSS "la t0, _bss_start",