From a908bcc0e4285ea464f738762f16dabc5efc7cbc Mon Sep 17 00:00:00 2001
From: gil <kalanggam@proton.me>
Date: Thu, 16 May 2024 11:47:44 -0500
Subject: [PATCH] Set `mstatus` and `mie` CSRs

---
 src/main.rs | 17 +++++++++++++++--
 1 file changed, 15 insertions(+), 2 deletions(-)

diff --git a/src/main.rs b/src/main.rs
index 7a841c3..e195052 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -39,8 +39,21 @@ unsafe extern "C" fn _enter() -> ! {
         // set the stack pointer
         "la sp, _init_stack_top",
 
-        "la t2, {trap_vector}",
-        "csrw mtvec, t2",
+        // We use mret here so that the mstatus register
+        // is properly updated.
+        "li t0, (0b11 << 11) | (1 << 7) | (1 << 3)",
+        "csrw mstatus, t0",
+        
+        // Set mtvec to the location of our trap handler function
+        "la t1, {trap_vector}",
+        "csrw mtvec, t1",
+
+        // Set MSIE, MTIE, and MEIE on machine interrupt enable CSR:
+        //   MSIE to enable machine-/M-mode software interrupts
+        //   MTIE to enable M-mode timer interrupts
+        //   MEIE to enable M-mode external interrupts
+        "li t2, (1 << 3) | (1 << 7) | (1 << 11)",
+        "csrw mie, t2",
 
         // clear the BSS
         "la t0, _bss_start",