diff --git a/src/main.rs b/src/main.rs
index 4135497..a298937 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -12,6 +12,7 @@ mod uart;
 #[no_mangle]
 #[link_section = ".text.init"]
 unsafe extern "C" fn _enter() -> ! {
+    // TODO see if possible to replace this somehow...
     use core::arch::asm;
     asm!(
         // load hartid into t0; if t0 =/= 0, then jump to busy loop
@@ -42,6 +43,11 @@ unsafe extern "C" fn _enter() -> ! {
         "bne t0, t1, 1b",
     "2:",
         // BSS is clear!
+
+        // delegate all traps to S-mode trap handler
+        "li t5, 0xffff",
+        "csrw medeleg, t5", // delegate all machine exceptions
+        "csrw mideleg, t5", // delegate all machine interrupts
         "j 4f",
     
     // busy loop if hartid =/= 0