Add trap.rs
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parent
be4bc6e270
commit
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17
src/main.rs
17
src/main.rs
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@ -6,6 +6,7 @@
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use core::panic::PanicInfo;
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mod heap;
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mod trap;
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mod uart;
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#[naked]
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@ -30,9 +31,17 @@ unsafe extern "C" fn _enter() -> ! {
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"la gp, _global_pointer",
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".option pop", // pops the current option stack
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// delegate all traps to S-mode trap handler
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"li t5, 0xffff",
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"csrw medeleg, t5", // delegate all machine exceptions
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"csrw mideleg, t5", // delegate all machine interrupts
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// set the stack pointer
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"la sp, _init_stack_top",
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"la t2, {trap_vector}",
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"csrw mtvec, t2",
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// clear the BSS
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"la t0, _bss_start",
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"la t1, _bss_end",
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@ -42,13 +51,8 @@ unsafe extern "C" fn _enter() -> ! {
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"addi t0, t0, 1",
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"bne t0, t1, 1b",
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"2:",
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// BSS is clear!
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// delegate all traps to S-mode trap handler
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"li t5, 0xffff",
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"csrw medeleg, t5", // delegate all machine exceptions
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"csrw mideleg, t5", // delegate all machine interrupts
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"j 4f",
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// BSS is clear!
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// busy loop if hartid =/= 0
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"3:",
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@ -59,6 +63,7 @@ unsafe extern "C" fn _enter() -> ! {
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// "tail-call" to {start} (call without saving a return address)
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"tail {start}",
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start = sym start, // {start} refers to the function [start] below
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trap_vector = sym trap::trap_handler, // {trap_vector} refers to function [trap::trap_handler]
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options(noreturn) // we must handle "returning" from assembly
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);
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}
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@ -38,7 +38,7 @@ SECTIONS {
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} >ram AT>ram :bss # and this goes into the bss segment
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. = ALIGN(16); # our stack needs to be 16-byte aligned, per the C calling convention
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PROVIDE(_init_stack_top = . + 0x1000); # reserve 0x1000 bytes for the initialisation stack
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PROVIDE(_init_stack_top = . + 0x1000); # reserve 0x1000 bytes (4 kB) for the initialisation stack
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PROVIDE(_kernel_heap_bottom = _init_stack_top); # allocate heap to remaining physical memory
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PROVIDE(_kernel_heap_top = ORIGIN(ram) + LENGTH(ram)); # top of heap is end of ram
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8
src/trap.rs
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8
src/trap.rs
Normal file
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@ -0,0 +1,8 @@
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#[naked]
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pub unsafe extern "C" fn trap_handler() -> ! {
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use core::arch::asm;
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asm!(
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"mret",
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options(noreturn)
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);
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}
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