From eab775e875792735299fec24df21dad05a7fe93f Mon Sep 17 00:00:00 2001
From: gil <kalanggam@proton.me>
Date: Fri, 17 May 2024 10:18:37 -0500
Subject: [PATCH] Comment result of inspecting disassembly

---
 src/main.rs | 34 +++++++++++++++++-----------------
 1 file changed, 17 insertions(+), 17 deletions(-)

diff --git a/src/main.rs b/src/main.rs
index 782be38..026a758 100644
--- a/src/main.rs
+++ b/src/main.rs
@@ -31,28 +31,28 @@ unsafe extern "C" fn _enter() -> ! {
         "la gp, _global_pointer",
         ".option pop", // pops the current option stack
 
-        // // delegate all traps to S-mode trap handler
-        // "li t5, 0xffff",
-        // "csrw medeleg, t5", // delegate all machine exceptions
-        // "csrw mideleg, t5", // delegate all machine interrupts
+        // delegate all traps to S-mode trap handler
+        "li t5, 0xffff",
+        "csrw medeleg, t5", // delegate all machine exceptions
+        "csrw mideleg, t5", // delegate all machine interrupts
 
         // set the stack pointer
         "la sp, _init_stack_top",
 
-        // // Make sure machine mode is set, and enable coarse interrupts
-        // "li t0, (0b11 << 11) | (1 << 7) | (1 << 3)",
-        // "csrw mstatus, t0",
+        // Make sure machine mode is set, and enable coarse interrupts
+        "li t0, (0b11 << 11) | (1 << 7) | (1 << 3)",
+        "csrw mstatus, t0",
         
-        // // Set mtvec to the location of our trap handler function
-        // "la t1, {trap_vector}",
-        // "csrw mtvec, t1",
+        // Set mtvec to the location of our trap handler function
+        "la t1, {trap_vector}",
+        "csrw mtvec, t1",
 
-        // // Set MSIE, MTIE, and MEIE on machine interrupt enable CSR:
-        // //   MSIE to enable machine-/M-mode software interrupts
-        // //   MTIE to enable M-mode timer interrupts
-        // //   MEIE to enable M-mode external interrupts
-        // "li t2, (1 << 3) | (1 << 7) | (1 << 11)",
-        // "csrw mie, t2",
+        // Set MSIE, MTIE, and MEIE on machine interrupt enable CSR:
+        //   MSIE to enable machine-/M-mode software interrupts
+        //   MTIE to enable M-mode timer interrupts
+        //   MEIE to enable M-mode external interrupts
+        //"li t2, (1 << 3) | (1 << 7) | (1 << 11)", 
+        //"csrw mie, t2", -> This is causing problems - after setting this register the kernel hangs
 
         // clear the BSS
         "la t0, _bss_start",
@@ -75,7 +75,7 @@ unsafe extern "C" fn _enter() -> ! {
         // "tail-call" to {start} (call without saving a return address)
         "tail {start}",
         start = sym start, // {start} refers to the function [start] below
-        //trap_vector = sym trap::trap_handler, // {trap_vector} refers to function [trap::trap_handler]
+        trap_vector = sym trap::trap_handler, // {trap_vector} refers to function [trap::trap_handler]
         options(noreturn) // we must handle "returning" from assembly
     );
 }