Set mstatus and mie CSRs

src/main.rs

@@ -39,8 +39,21 @@ unsafe extern "C" fn _enter() -> ! {
         // set the stack pointer
         "la sp, _init_stack_top",
 
-        "la t2, {trap_vector}",
+        // We use mret here so that the mstatus register
-        "csrw mtvec, t2",
+        // is properly updated.
+        "li t0, (0b11 << 11) | (1 << 7) | (1 << 3)",
+        "csrw mstatus, t0",
+        
+        // Set mtvec to the location of our trap handler function
+        "la t1, {trap_vector}",
+        "csrw mtvec, t1",
+
+        // Set MSIE, MTIE, and MEIE on machine interrupt enable CSR:
+        //   MSIE to enable machine-/M-mode software interrupts
+        //   MTIE to enable M-mode timer interrupts
+        //   MEIE to enable M-mode external interrupts
+        "li t2, (1 << 3) | (1 << 7) | (1 << 11)",
+        "csrw mie, t2",
 
         // clear the BSS
         "la t0, _bss_start",
@@ -96,12 +109,24 @@ extern "C" fn start() -> ! {
     }
 }
 
-#[panic_handler]
+#[no_mangle]
-fn on_panic(info: &PanicInfo) -> ! {
+extern "C" fn eh_personality() {}
-    // print panic info and hang
-    println!("{}", info);
 
-    loop {}
+#[panic_handler]
+fn panic(info: &PanicInfo) -> ! {
+    // print panic info and abort
+    println!("{}", info);
+    abort();
+}
+
+#[no_mangle]
+extern "C" fn abort() -> ! {
+    use core::arch::asm;
+    loop {
+        unsafe {
+            asm!("wfi");
+        }
+    }
 }
 
 // TODO unit testing