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Author SHA1 Message Date
gil a908bcc0e4 Set mstatus and mie CSRs 2024-05-16 11:47:44 -05:00
gil 6b697a4ca5 Add abort & update panic handler 2024-05-16 11:38:01 -05:00

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@ -39,8 +39,21 @@ unsafe extern "C" fn _enter() -> ! {
// set the stack pointer
"la sp, _init_stack_top",
"la t2, {trap_vector}",
"csrw mtvec, t2",
// We use mret here so that the mstatus register
// is properly updated.
"li t0, (0b11 << 11) | (1 << 7) | (1 << 3)",
"csrw mstatus, t0",
// Set mtvec to the location of our trap handler function
"la t1, {trap_vector}",
"csrw mtvec, t1",
// Set MSIE, MTIE, and MEIE on machine interrupt enable CSR:
// MSIE to enable machine-/M-mode software interrupts
// MTIE to enable M-mode timer interrupts
// MEIE to enable M-mode external interrupts
"li t2, (1 << 3) | (1 << 7) | (1 << 11)",
"csrw mie, t2",
// clear the BSS
"la t0, _bss_start",
@ -96,12 +109,24 @@ extern "C" fn start() -> ! {
}
}
#[panic_handler]
fn on_panic(info: &PanicInfo) -> ! {
// print panic info and hang
println!("{}", info);
#[no_mangle]
extern "C" fn eh_personality() {}
loop {}
#[panic_handler]
fn panic(info: &PanicInfo) -> ! {
// print panic info and abort
println!("{}", info);
abort();
}
#[no_mangle]
extern "C" fn abort() -> ! {
use core::arch::asm;
loop {
unsafe {
asm!("wfi");
}
}
}
// TODO unit testing