Go to file
2024-05-20 03:03:25 -05:00
.cargo Call Rust from assembly instead, relocate linker script 2024-05-19 20:03:03 -05:00
.vscode Initial commit 2024-05-13 17:31:37 -05:00
lds Update entry code, switch to spin crate for spinlocks 2024-05-20 02:35:16 -05:00
src Update entry code, switch to spin crate for spinlocks 2024-05-20 02:35:16 -05:00
.gitignore Initial commit 2024-05-13 17:31:37 -05:00
20240519-kernel_init_diagram.png Update readme and init 2024-05-19 17:42:50 -05:00
20240520-kernel_init_diagram.png Update flowchart 2024-05-20 03:03:25 -05:00
build.rs Call Rust from assembly instead, relocate linker script 2024-05-19 20:03:03 -05:00
Cargo.lock Update entry code, switch to spin crate for spinlocks 2024-05-20 02:35:16 -05:00
Cargo.toml Update entry code, switch to spin crate for spinlocks 2024-05-20 02:35:16 -05:00
README.md Update flowchart 2024-05-20 03:03:25 -05:00
RESOURCES.md Update readme and init 2024-05-19 17:42:50 -05:00

created modified
2024-05-13T14:28:49-05:00 2024-05-19T17:41:01-05:00

kernel

A kernel for RISC-V written in Rust. Currently focused on running on QEMU generic riscv64, advice and assistance welcome & encouraged.

Progress

  • 2024-05-19: As of right now, the basic "stuff" for initializing the kernel is there. The diagram below shows what I'm thinking as far as what the init process should be. This is what I'm currently working on implementing, and I will update this chart (and prettify it) more

  • 2024-05-20: I added entry.S and entry_alt.S, its planned replacement, and rewrote some of the code. I also switched from using the spinning_top crate to spin, since spinning_top did not have out-of-the-box support for a one-time spinlock. Here is a new flowchart, replacing the previous one, showing what the kernel init process is:

A flowchart showing the kernel initialization process. On the left column are hart 0-specific steps, on the right are steps for other harts. The first stage happens in the _entry code. 1. Setting global, stack, and thread pointers. 2. Initializing the BSS (main hart only). The second stage shows the start code, where both the main hart and the other harts prepare CSRs for S-mode interrupts. This stage is also where PMP and timers would be set up. The final stage is for the main function, where the main hart (hart 0) initializes the console, paging system, processing system, and interrupts before the first user process. While hart 0 is initializing, the other harts wait for it to finish. Once hart 0 is done, the other harts will enable paging and interrupts, and all harts will enter the scheduler.

Research and implement

  • Basics
    • Processes
    • Virtual address spaces, page tables
    • Files, directories
    • Pipes
    • Multitasking, time-slicing
    • Syscalls
  • CPU cache
  • User authentication, login
  • File protection, permissions
  • Mountable file systems
  • Paging to disk
  • Sockets, network support
  • Interprocess communication
  • Device drivers
  • User applications

Resources

See RESOURCES.md