Enable other cores and rewrite init step

.cargo/config.toml

@@ -18,6 +18,7 @@ target = "riscv64imac-unknown-none-elf"
 [target.riscv64imac-unknown-none-elf]
 runner = """ qemu-system-riscv64
   -cpu rv64
+  -smp 4
   -machine virt
   -m 150M
   -s

src/main.rs

@@ -16,9 +16,10 @@ unsafe extern "C" fn _enter() -> ! {
     // TODO see if possible to replace this somehow...
     use core::arch::asm;
     asm!(
-        // load hartid into t0; if t0 =/= 0, then jump to busy loop
-        "csrr t0, mhartid",
-        "bnez t0, 3f",
+        // load hartid into `tp``
+        // if hartid =/= 0, then jump to busy loop
+        "csrr tp, mhartid",
+        "bnez tp, 3f",
 
         // before we use the `la` pseudo-instruction for the first time,
         // we need to set `gp` (look up linker relaxation)