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Enable other cores and rewrite init step

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gil 2024-05-18 08:00:48 -05:00
parent bc6cc35725
commit 20c0841a89
2 changed files with 5 additions and 3 deletions
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1
.cargo/config.toml
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@ -18,6 +18,7 @@ target = "riscv64imac-unknown-none-elf"
[target.riscv64imac-unknown-none-elf] [target.riscv64imac-unknown-none-elf]
runner = """ qemu-system-riscv64 runner = """ qemu-system-riscv64
-cpu rv64 -cpu rv64
-smp 4
-machine virt -machine virt
-m 150M -m 150M
-s -s

7
src/main.rs
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@ -16,9 +16,10 @@ unsafe extern "C" fn _enter() -> ! {
// TODO see if possible to replace this somehow... // TODO see if possible to replace this somehow...
use core::arch::asm; use core::arch::asm;
asm!( asm!(
// load hartid into t0; if t0 =/= 0, then jump to busy loop // load hartid into `tp``
"csrr t0, mhartid", // if hartid =/= 0, then jump to busy loop
"bnez t0, 3f", "csrr tp, mhartid",
"bnez tp, 3f",
// before we use the `la` pseudo-instruction for the first time, // before we use the `la` pseudo-instruction for the first time,
// we need to set `gp` (look up linker relaxation) // we need to set `gp` (look up linker relaxation)