Rewrite some asm with riscv crate
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304152dbeb
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18
src/entry.rs
18
src/entry.rs
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@ -1,8 +1,12 @@
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// src/entry.rs
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// src/entry.rs
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use riscv::register::mepc;
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#[no_mangle]
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#[no_mangle]
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#[link_section = ".text.init"]
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#[link_section = ".text.init"]
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unsafe extern "C" fn _entry() {
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unsafe extern "C" fn _entry() {
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use core::arch::asm;
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use core::arch::asm;
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use riscv::register::{mhartid, satp, mstatus, sstatus};
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// let id = riscv::register::mhartid::read();
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// let id = riscv::register::mhartid::read();
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// write_tp(&id);
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// write_tp(&id);
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// TODO set up stack for all harts
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// TODO set up stack for all harts
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@ -29,9 +33,9 @@ unsafe extern "C" fn _entry() {
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".option pop",
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".option pop",
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);
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);
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riscv::register::satp::write(0);
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satp::write(0);
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let id = riscv::register::mhartid::read();
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let id = mhartid::read();
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if id != 0 { crate::abort(); }
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if id != 0 { crate::abort(); }
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// Clear BSS section
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// Clear BSS section
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@ -45,10 +49,13 @@ unsafe extern "C" fn _entry() {
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"bne t0, t1, 1b",
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"bne t0, t1, 1b",
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"2:",
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"2:",
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"la sp, _stack_end",
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"la sp, _stack_end"
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);
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"li t0, (0b11 << 11) | (1 << 13)",
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mstatus::set_mpp(mstatus::MPP::Machine);
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"csrw mstatus, t0",
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mstatus::set_fs(sstatus::FS::Initial);
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asm!(
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"csrw mie, x0",
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"csrw mie, x0",
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"la t1, {kinit}",
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"la t1, {kinit}",
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@ -59,6 +66,7 @@ unsafe extern "C" fn _entry() {
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"2:",
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"2:",
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kinit = sym kinit,
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kinit = sym kinit,
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);
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);
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}
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}
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#[no_mangle]
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#[no_mangle]
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