gil/kernel
1
0
Fork 0
Code Issues Pull requests Actions Packages Projects Releases Wiki Activity

Make init lock less ambiguous, add fences

Browse source
This commit is contained in:
gil 2024-05-20 09:42:25 -05:00
parent 325fa3c147
commit eee7c6f02b
1 changed files with 5 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
src/entry.rs
View file

@ -1,6 +1,6 @@
// src/entry.rs // src/entry.rs
static READY: spin::Once<()> = spin::Once::new(); static INIT_LOCK: spin::Once<()> = spin::Once::new();
/// After some initialization in asm/entry.S, the kernel will jump here and /// After some initialization in asm/entry.S, the kernel will jump here and
/// each hart will have its own setup sequence. /// each hart will have its own setup sequence.
@ -42,7 +42,7 @@ extern "C" fn main() {
use riscv::register::{mstatus, sstatus}; use riscv::register::{mstatus, sstatus};
if hartid() == 0 { if hartid() == 0 {
READY.call_once(|| { INIT_LOCK.call_once(|| {
// Disable machine interrupts while initializing // Disable machine interrupts while initializing
interrupt::machine::disable(); interrupt::machine::disable();
// TODO Initialize console // TODO Initialize console
@ -62,10 +62,11 @@ extern "C" fn main() {
mstatus::set_fs(sstatus::FS::Initial); mstatus::set_fs(sstatus::FS::Initial);
} }
riscv::asm::fence(); riscv::asm::fence(); // Emit a fence just in case
}); });
} else { } else {
READY.wait(); INIT_LOCK.wait();
riscv::asm::fence(); // Emit a fence just in case
kinit_hart(); kinit_hart();
} }
} }