 gil
|
1b90501975
|
Realign
|
2024-05-17 10:55:43 -05:00 |
|
|
gil
|
7f183c7712
|
Fixed kernel hanging by disabling timer interrupts
|
2024-05-17 10:40:55 -05:00 |
|
|
gil
|
eab775e875
|
Comment result of inspecting disassembly
|
2024-05-17 10:18:37 -05:00 |
|
|
gil
|
2bce140e57
|
Just inlining some statements
|
2024-05-17 09:54:07 -05:00 |
|
|
gil
|
391b13a314
|
Troubleshooting issue with setting CSRs
|
2024-05-16 12:30:03 -05:00 |
|
|
gil
|
3827beec26
|
Correction to prev comment
|
2024-05-16 12:21:33 -05:00 |
|
|
gil
|
a908bcc0e4
|
Set mstatus and mie CSRs
|
2024-05-16 11:47:44 -05:00 |
|
|
gil
|
6b697a4ca5
|
Add abort & update panic handler
|
2024-05-16 11:38:01 -05:00 |
|
|
gil
|
c70be3fe1f
|
Add trap.rs
|
2024-05-16 11:21:27 -05:00 |
|
|
gil
|
be4bc6e270
|
Add to-do and set interrupt CSRs
|
2024-05-16 10:39:53 -05:00 |
|
|
gil
|
aaf64d0a2d
|
Add a comment
|
2024-05-16 08:23:08 -05:00 |
|
|
gil
|
ef07d172ff
|
Regroup asm blocks
|
2024-05-16 08:21:50 -05:00 |
|
|
gil
|
8c1f860d25
|
Degoogle lol
|
2024-05-16 08:19:23 -05:00 |
|
|
gil
|
5df0472703
|
Loop for non-0 hartid's
|
2024-05-16 08:19:15 -05:00 |
|
|
gil
|
9aa8460825
|
Cleaning up a comment
|
2024-05-16 00:50:35 -05:00 |
|
|
gil
|
b78f21ed21
|
Comment out unused code blocks
|
2024-05-16 00:37:21 -05:00 |
|
|
gil
|
6846ecbcc0
|
Print hartid after hello world
|
2024-05-16 00:36:19 -05:00 |
|
|
gil
|
1644d5a068
|
Add riscv crate
|
2024-05-16 00:18:11 -05:00 |
|
|
gil
|
7d658ad704
|
explain some of the .option directives in _enter()
|
2024-05-15 23:33:36 -05:00 |
|
|
gil
|
e409015ff8
|
Remove extra braces
|
2024-05-15 23:17:55 -05:00 |
|
|
gil
|
2b80cb9a9b
|
Add comment from memmap
|
2024-05-15 23:17:35 -05:00 |
|
|
gil
|
13fb110417
|
Printing from panic handler
|
2024-05-15 23:13:10 -05:00 |
|
|
gil
|
ae7b904abc
|
Use _enter for program entrypoint instead of _start, and change entry to start
|
2024-05-15 20:44:54 -05:00 |
|
|
gil
|
8cfd1c245a
|
Update readme
|
2024-05-14 12:11:54 -05:00 |
|
|
gil
|
7cd1869f20
|
Updated README
|
2024-05-14 11:12:11 -05:00 |
|
|
gil
|
9bb75720c5
|
Removed redundant stack pointer initialization from _start
|
2024-05-14 10:09:16 -05:00 |
|
|
gil
|
4c3bfa3052
|
Reindent
|
2024-05-14 10:06:57 -05:00 |
|
|
gil
|
c22e3e4376
|
Initializing heap
|
2024-05-14 10:03:08 -05:00 |
|
|
gil
|
f43f41800f
|
Commented out riscv32 target
|
2024-05-14 09:43:38 -05:00 |
|
|
gil
|
3e197b9882
|
Rename project and change target to riscv64imac
|
2024-05-14 09:41:57 -05:00 |
|
|
gil
|
7c7bb75d4c
|
Clarify comment in build script
|
2024-05-14 00:05:58 -05:00 |
|
|
gil
|
e1ea4cc21c
|
Update build script convention to change from cargo: (deprecated) to cargo::
|
2024-05-13 23:08:09 -05:00 |
|
|
gil
|
41a450393e
|
Add rx ability to uart
|
2024-05-13 22:59:41 -05:00 |
|
|
gil
|
5490a2ffd6
|
Add disclaimer
|
2024-05-13 22:14:16 -05:00 |
|
|
gil
|
fc7eb5dfce
|
Create module uart
|
2024-05-13 22:12:29 -05:00 |
|
|
gil
|
556a9841e5
|
Prints 'Hello World'
|
2024-05-13 22:07:46 -05:00 |
|
|
gil
|
78f93533a4
|
Prettifying
|
2024-05-13 21:42:49 -05:00 |
|
|
gil
|
78ba8f22a6
|
Add links to RISC-V spec pdfs
|
2024-05-13 21:37:28 -05:00 |
|
|
gil
|
2cce36b132
|
Added more readings
|
2024-05-13 17:39:00 -05:00 |
|
|
gil
|
63a2a76b0b
|
Initial commit
|
2024-05-13 17:31:37 -05:00 |
|