 gil
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304152dbeb
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Trim unnecessary unsafe blocks
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2024-05-18 23:22:04 -05:00 |
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gil
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e7060b38bd
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Minor comment tweak
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2024-05-18 21:11:03 -05:00 |
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gil
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9e180a565a
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Rewrite heap allocation and linker section
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2024-05-18 21:09:22 -05:00 |
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gil
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c7ccdc371d
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Update linker script
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2024-05-18 20:02:40 -05:00 |
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gil
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1ff52acc42
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Add some todos
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2024-05-18 09:35:00 -05:00 |
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gil
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9af10f2a8e
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Begin rewriting entry
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2024-05-18 09:26:17 -05:00 |
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gil
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20c0841a89
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Enable other cores and rewrite init step
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2024-05-18 08:00:48 -05:00 |
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gil
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bc6cc35725
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Add another good site to readings
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2024-05-18 00:15:18 -05:00 |
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gil
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531f0b8a59
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Restore important part of example comment
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2024-05-18 00:07:42 -05:00 |
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gil
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1b90501975
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Realign
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2024-05-17 10:55:43 -05:00 |
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gil
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7f183c7712
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Fixed kernel hanging by disabling timer interrupts
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2024-05-17 10:40:55 -05:00 |
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gil
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eab775e875
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Comment result of inspecting disassembly
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2024-05-17 10:18:37 -05:00 |
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gil
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2bce140e57
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Just inlining some statements
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2024-05-17 09:54:07 -05:00 |
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gil
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391b13a314
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Troubleshooting issue with setting CSRs
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2024-05-16 12:30:03 -05:00 |
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gil
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3827beec26
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Correction to prev comment
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2024-05-16 12:21:33 -05:00 |
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gil
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a908bcc0e4
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Set mstatus and mie CSRs
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2024-05-16 11:47:44 -05:00 |
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gil
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6b697a4ca5
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Add abort & update panic handler
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2024-05-16 11:38:01 -05:00 |
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gil
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c70be3fe1f
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Add trap.rs
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2024-05-16 11:21:27 -05:00 |
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gil
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be4bc6e270
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Add to-do and set interrupt CSRs
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2024-05-16 10:39:53 -05:00 |
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gil
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aaf64d0a2d
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Add a comment
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2024-05-16 08:23:08 -05:00 |
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gil
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ef07d172ff
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Regroup asm blocks
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2024-05-16 08:21:50 -05:00 |
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gil
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8c1f860d25
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Degoogle lol
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2024-05-16 08:19:23 -05:00 |
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gil
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5df0472703
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Loop for non-0 hartid's
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2024-05-16 08:19:15 -05:00 |
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gil
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9aa8460825
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Cleaning up a comment
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2024-05-16 00:50:35 -05:00 |
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gil
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b78f21ed21
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Comment out unused code blocks
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2024-05-16 00:37:21 -05:00 |
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gil
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6846ecbcc0
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Print hartid after hello world
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2024-05-16 00:36:19 -05:00 |
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gil
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1644d5a068
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Add riscv crate
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2024-05-16 00:18:11 -05:00 |
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gil
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7d658ad704
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explain some of the .option directives in _enter()
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2024-05-15 23:33:36 -05:00 |
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gil
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e409015ff8
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Remove extra braces
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2024-05-15 23:17:55 -05:00 |
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gil
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2b80cb9a9b
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Add comment from memmap
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2024-05-15 23:17:35 -05:00 |
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gil
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13fb110417
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Printing from panic handler
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2024-05-15 23:13:10 -05:00 |
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gil
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ae7b904abc
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Use _enter for program entrypoint instead of _start, and change entry to start
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2024-05-15 20:44:54 -05:00 |
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gil
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8cfd1c245a
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Update readme
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2024-05-14 12:11:54 -05:00 |
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gil
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7cd1869f20
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Updated README
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2024-05-14 11:12:11 -05:00 |
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gil
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9bb75720c5
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Removed redundant stack pointer initialization from _start
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2024-05-14 10:09:16 -05:00 |
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gil
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4c3bfa3052
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Reindent
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2024-05-14 10:06:57 -05:00 |
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gil
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c22e3e4376
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Initializing heap
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2024-05-14 10:03:08 -05:00 |
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gil
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f43f41800f
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Commented out riscv32 target
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2024-05-14 09:43:38 -05:00 |
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gil
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3e197b9882
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Rename project and change target to riscv64imac
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2024-05-14 09:41:57 -05:00 |
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gil
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7c7bb75d4c
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Clarify comment in build script
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2024-05-14 00:05:58 -05:00 |
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gil
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e1ea4cc21c
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Update build script convention to change from cargo: (deprecated) to cargo::
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2024-05-13 23:08:09 -05:00 |
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gil
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41a450393e
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Add rx ability to uart
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2024-05-13 22:59:41 -05:00 |
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gil
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5490a2ffd6
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Add disclaimer
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2024-05-13 22:14:16 -05:00 |
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gil
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fc7eb5dfce
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Create module uart
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2024-05-13 22:12:29 -05:00 |
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gil
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556a9841e5
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Prints 'Hello World'
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2024-05-13 22:07:46 -05:00 |
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gil
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78f93533a4
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Prettifying
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2024-05-13 21:42:49 -05:00 |
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gil
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78ba8f22a6
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Add links to RISC-V spec pdfs
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2024-05-13 21:37:28 -05:00 |
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gil
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2cce36b132
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Added more readings
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2024-05-13 17:39:00 -05:00 |
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gil
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63a2a76b0b
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Initial commit
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2024-05-13 17:31:37 -05:00 |
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