gil
|
6f6f012be9
|
Trying to figure stuff out
|
2024-05-23 14:10:40 -05:00 |
|
gil
|
4edcebba18
|
Delete redundant entry code
|
2024-05-22 23:30:01 -05:00 |
|
gil
|
2aad0977f1
|
Switch to newly refactored init process, update readme
|
2024-05-21 15:17:15 -05:00 |
|
gil
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eee7c6f02b
|
Make init lock less ambiguous, add fences
|
2024-05-20 09:42:25 -05:00 |
|
gil
|
325fa3c147
|
Update flowchart
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2024-05-20 03:03:25 -05:00 |
|
gil
|
5dfd3f780f
|
Update entry code, switch to spin crate for spinlocks
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2024-05-20 02:35:16 -05:00 |
|
gil
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e5b51efb87
|
Call Rust from assembly instead, relocate linker script
|
2024-05-19 20:03:03 -05:00 |
|
gil
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d447232b0b
|
Tweak readme
|
2024-05-19 17:48:59 -05:00 |
|
gil
|
109afc7840
|
Fix bad link
|
2024-05-19 17:43:44 -05:00 |
|
gil
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d2560cca86
|
Update readme and init
|
2024-05-19 17:42:50 -05:00 |
|
gil
|
2cafa00346
|
Rewrite some asm with riscv crate
|
2024-05-18 23:37:16 -05:00 |
|
gil
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304152dbeb
|
Trim unnecessary unsafe blocks
|
2024-05-18 23:22:04 -05:00 |
|
gil
|
e7060b38bd
|
Minor comment tweak
|
2024-05-18 21:11:03 -05:00 |
|
gil
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9e180a565a
|
Rewrite heap allocation and linker section
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2024-05-18 21:09:22 -05:00 |
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gil
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c7ccdc371d
|
Update linker script
|
2024-05-18 20:02:40 -05:00 |
|
gil
|
1ff52acc42
|
Add some todos
|
2024-05-18 09:35:00 -05:00 |
|
gil
|
9af10f2a8e
|
Begin rewriting entry
|
2024-05-18 09:26:17 -05:00 |
|
gil
|
20c0841a89
|
Enable other cores and rewrite init step
|
2024-05-18 08:00:48 -05:00 |
|
gil
|
bc6cc35725
|
Add another good site to readings
|
2024-05-18 00:15:18 -05:00 |
|
gil
|
531f0b8a59
|
Restore important part of example comment
|
2024-05-18 00:07:42 -05:00 |
|
gil
|
1b90501975
|
Realign
|
2024-05-17 10:55:43 -05:00 |
|
gil
|
7f183c7712
|
Fixed kernel hanging by disabling timer interrupts
|
2024-05-17 10:40:55 -05:00 |
|
gil
|
eab775e875
|
Comment result of inspecting disassembly
|
2024-05-17 10:18:37 -05:00 |
|
gil
|
2bce140e57
|
Just inlining some statements
|
2024-05-17 09:54:07 -05:00 |
|
gil
|
391b13a314
|
Troubleshooting issue with setting CSRs
|
2024-05-16 12:30:03 -05:00 |
|
gil
|
3827beec26
|
Correction to prev comment
|
2024-05-16 12:21:33 -05:00 |
|
gil
|
a908bcc0e4
|
Set mstatus and mie CSRs
|
2024-05-16 11:47:44 -05:00 |
|
gil
|
6b697a4ca5
|
Add abort & update panic handler
|
2024-05-16 11:38:01 -05:00 |
|
gil
|
c70be3fe1f
|
Add trap.rs
|
2024-05-16 11:21:27 -05:00 |
|
gil
|
be4bc6e270
|
Add to-do and set interrupt CSRs
|
2024-05-16 10:39:53 -05:00 |
|
gil
|
aaf64d0a2d
|
Add a comment
|
2024-05-16 08:23:08 -05:00 |
|
gil
|
ef07d172ff
|
Regroup asm blocks
|
2024-05-16 08:21:50 -05:00 |
|
gil
|
8c1f860d25
|
Degoogle lol
|
2024-05-16 08:19:23 -05:00 |
|
gil
|
5df0472703
|
Loop for non-0 hartid's
|
2024-05-16 08:19:15 -05:00 |
|
gil
|
9aa8460825
|
Cleaning up a comment
|
2024-05-16 00:50:35 -05:00 |
|
gil
|
b78f21ed21
|
Comment out unused code blocks
|
2024-05-16 00:37:21 -05:00 |
|
gil
|
6846ecbcc0
|
Print hartid after hello world
|
2024-05-16 00:36:19 -05:00 |
|
gil
|
1644d5a068
|
Add riscv crate
|
2024-05-16 00:18:11 -05:00 |
|
gil
|
7d658ad704
|
explain some of the .option directives in _enter()
|
2024-05-15 23:33:36 -05:00 |
|
gil
|
e409015ff8
|
Remove extra braces
|
2024-05-15 23:17:55 -05:00 |
|
gil
|
2b80cb9a9b
|
Add comment from memmap
|
2024-05-15 23:17:35 -05:00 |
|
gil
|
13fb110417
|
Printing from panic handler
|
2024-05-15 23:13:10 -05:00 |
|
gil
|
ae7b904abc
|
Use _enter for program entrypoint instead of _start , and change entry to start
|
2024-05-15 20:44:54 -05:00 |
|
gil
|
8cfd1c245a
|
Update readme
|
2024-05-14 12:11:54 -05:00 |
|
gil
|
7cd1869f20
|
Updated README
|
2024-05-14 11:12:11 -05:00 |
|
gil
|
9bb75720c5
|
Removed redundant stack pointer initialization from _start
|
2024-05-14 10:09:16 -05:00 |
|
gil
|
4c3bfa3052
|
Reindent
|
2024-05-14 10:06:57 -05:00 |
|
gil
|
c22e3e4376
|
Initializing heap
|
2024-05-14 10:03:08 -05:00 |
|
gil
|
f43f41800f
|
Commented out riscv32 target
|
2024-05-14 09:43:38 -05:00 |
|
gil
|
3e197b9882
|
Rename project and change target to riscv64imac
|
2024-05-14 09:41:57 -05:00 |
|